The present invention relates to a nonvolatile memory device, and more particularly, to a memory device using a ferroelectric material.
Ferroelectric memory is nonvolatile memory utilizing a feature that polarization generated along the direction of an electric field applied to a ferroelectric film remains even after removal of the electric field. Such memory is finding applications as nonvolatile memories for IC cards and the like that require high speed and a large number of times of rewrite in encryption processing and the like.
FIG. 7 is a circuit diagram of a ferroelectric memory cell. In FIG. 7, WL denotes a word line, BL a bit line, MT a selection transistor that is a MOS transistor, MC a ferroelectric capacitor, PL a plate line, and SN a storage node. One electrode constituting the ferroelectric capacitor MC, that is, the plate line PL is shared with a ferroelectric capacitor of another memory cell. The other electrode of the ferroelectric capacitor MC, that is, the storage node SN is connected to the source electrode of the selection transistor MT. The gate electrode and drain electrode of the selection transistor MT are connected to the word line WL and the bit line BL, respectively.
FIG. 8 shows a hysteresis characteristic representing the polarization characteristic of the ferroelectric capacitor MC, in which the x-axis represents the voltage V and the y-axis represents the polarization Q.
FIG. 9 is a control timing chart in one cycle of the ferroelectric memory cell of FIG. 7. It is assumed in this chart that another ferroelectric capacitor sharing the plate line PL is connected to a complementary bit line /BL and that a sense amplifier is further provided which is activated with a signal SAE and amplifies the potential difference between the bit lines BL and /BL.
The operation of the ferroelectric memory will be described with reference to FIGS. 8 and 9. At time t0, data “1” and “0” are respectively in the states of point a and point e in FIG. 8. At time t1, a voltage Vcc is applied to the plate line PL, and at time t2, data “1” and “0” have respectively moved to the states of point b and point f. At time t3, the sense amplifier is started, and at time t4, data “1” and “0” have respectively moved to the states of point c and point g. These states continue until time t5. At time t5, the voltage of the plate line PL is lowered from Vcc to 0 V, and data “1” and “0” have respectively moved to the states of point d and point e. These states continue until time t6. At time t6, at which the driving of the sense amplifier is cut off, data “1” and “0” respectively return to the original states of point a and point e in FIG. 8.
The ferroelectric memory involves destructive read in its read operation, and thus rewrite operation is necessary after read operation. The operation of point c to point d and to point a and the operation of point f to point g and to point e are called rewrite operation. Due to this operation, the ferroelectric film becomes fatigued, and thus a limitation similar to that on the number of times of rewrite is also imposed on the number of times of read.
To solve the problem of deterioration of the life due to fatigue, a ferroelectric memory called shadow RAM has been proposed. The shadow RAM operates in volatile mode like DRAM during normal operation, and converts volatile information to nonvolatile information at the time of power-off while converting nonvolatile information to volatile information at the time of power-on.
In Japanese Laid-Open Patent Publication No. 3-5996 and U.S. Pat. No. 5,297,077, nonvolatile mode and volatile mode are established by changing the potential at a plate line or the drive method thereof.
In U.S. Pat. No. 5,455,786, a plate line is held at the same potential in both nonvolatile mode and volatile mode so that volatile write also serves as nonvolatile write, and that polarization reversal can be effectively prevented during read in the volatile mode. During the time of power-off, the potential at the plate line is speedily dropped.
In U.S. Pat. No. 5,910,911, while a plate line is held at the same potential in both nonvolatile mode and volatile mode, the data amplitude at a bit line is made large in the nonvolatile mode and small in the volatile mode.
The shadow RAM technology described above has the following problems. It is necessary to covert volatile information to nonvolatile information at the time of power-off and convert nonvolatile information to volatile information at the time of power-on. Also, since the power supply voltage decreases with achievement of finer process rules, it is becoming difficult to establish a polarized state with write under an electric field lower than a coercive electric field.